Distributed systems may require to synchronize between devices that are fed by different clock signals. IEEE standard 1588 is an example of a cost effective and high accuracy synchronization method. A typical 1588 IEEE compliant device is illustrated in FIG. 1 while a 1588 IEEE synchronization sequence is illustrated in FIG. 2.
Device 70 includes software and hardware components. The software components includes a precise time protocol (PTP) application 30 that can interface with various hardware components via port interface 32, timestamp interface 34 and clock interface.
Device 70 can receive and transmit information by using multiple protocol layer components such as network protocol stack 40, media access controller 42 and physical layer (PHY layer) 44. The network protocol stack can include TCP/IP/Ethernet compliant components.
A real time clock generator 60 generates a sequence of timestamps. These timestamps can be sent via clock interface 36 to PTP application and can also be sent to timestamp unit 50 that is capable of sampling these clock samples when it detects (the TSU sample the timestamp for all kind of frames at the start frame delimiter and use it only if the frame is considered as PTP frame which requires a timestamp) a timing information frame, and especially when it detects a start frame delimiter within a timing information frame. A typical timing information frame includes a preamble, a start of frame delimiter, a destination address, a source address, a frame type/length information, UDP header, PTP message (timing information) and a error correction field.
The timestamp unit 50 monitors a MAC layer-PHY layer interface such as MAC-PHY bus(e.g MII interface) 43 and when it detects that start frame delimiter passes over said bus it samples the timestamp that is provided by real time clock generator 60 and if the received frame is deemed to be a valid timing information frame then is sends an interrupt to a processor (not shown) that in turn extracts the timing information and can perform a synchronization sequence.
FIG. 2 illustrates a prior art synchronization sequence between a master device and a slave device. IEEE1588 also provides a mechanism that determines which device should be regarded as a master device that provides a master clock and which device is regarded as a slave device that provides a slave clock. The slave clock has to be adjusted according to the master clock.
The master device is illustrated by PTP application 30 and by MAC-PHY bus 43, while the slave device is illustrated by PTP application 30′ and by MAC-PHY bus 43′.
The synchronization sequence starts includes an offset determination phase (illustrated by arrows 80 and 82) and a delay measurement phase (illustrated by arrows 84 and 86).
The offset measurement phase starts (as illustrated by arrow 80) by transmitting a synchronization frame that includes an estimated transmission time of that frame. The transmission occurs at T0 and the slave device receives the frame (at MAC-PHY interface 43′) at exact point in time T1. Arrow 82 indicates that the master device then sends another frame (“follow up frame”) that includes the exact transmission time (T0).
The slave device receives the follow up frame and can determine the offset between the slave clock and the master clock.
The delay measurement phase starts by (as illustrated by arrow 84) a transmission of a delay request frame from the slave device to the master device. This frame is transmitted from the slave device at point of time T2 and is received at the master device at point of time T3. The master device then transmits a delay response frame (illustrated by arrow 86) that includes point of time T3.
The difference between point of time T2 and T3 represent the propagation delay between the devices. This delay can be calculated by the slave device.
There is a need to provide efficient methods for receiving and processing frames and to provide efficient devices that have frame receiving and processing capabilities.